Modern electronic devices (e.g., laptops, computers, smart phones, tablets, and the like) are sequential state machines that perform various logical operations using combinations of logic gates. The prevalence of these modern electronic devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements of electronic devices and generates a need for more power-efficient devices. Accordingly, there is increasing pressure to continue miniaturizing logic gates and to reduce their power consumption. Miniaturization of components impacts all aspects of processing circuitry, including transistors and other reactive elements in the processing circuitry, such as metal oxide semiconductors (MOSs). MOS devices generally provide logic gates through combinations of transistors.
Historically, MOS devices have benefited from increasing miniaturization efforts. In the past, such semiconductor miniaturization not only reduced the footprint area occupied by the MOS devices in an integrated circuit (IC), but also reduced the power required to operate such ICs, thereby concurrently improving operating speeds. As the MOS devices were reduced to a nanometer scale (e.g., a ninety (90) nanometer scale), the footprint area occupied by the MOS devices in the IC was reduced, as expected. However, the MOS devices could not operate at an appreciably faster speed, because the mobility of the current mechanism (i.e., electrons or holes) did not also improve linearly, since mobility is a function of the effective mass of the current mechanism, and the effective mass was not changed with miniaturization.
Various techniques have been implemented to attempt to improve the speed with which transistor-based logic gates operate in the nanometer scale. Unfortunately, these techniques are problematic, as transistors have proved difficult to control. Furthermore, transistor-based logic gates continue to present power consumption problems as increases in transistor density have not introduced linear savings in power consumption. Transistor-based logic gates may thus be quickly reaching their design limits, and other types of technologies may be needed to continue the miniaturization of ICs. Thus, an effective technique is needed for creating logic gates and performing logical operations that are better adapted at the nanometer scale and are more power-efficient than current transistor-based technology.
In order to combat the aforementioned problems, spintronic logic gates employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) are being developed for performing logical operations. In general, the GSHE MTJ elements include a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a top electrode of the MTJ coupled to a third terminal (C). A magnetization of an easy axis of the free layer of the MTJ is substantially perpendicular to the magnetization direction created by electrons traversing the GSHE strip between the first terminal (A) and the second terminal (B), such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected or extracted (i.e., positive/negative current directions) through the third terminal (C) into or out of the MTJ through the top electrode.
Spintronic logic gates formed from the GSHE MTJ elements have been shown to provide for greater power efficiency than transistor-based logic gates. Also, the spintronic logic gates are capable of being disposed in a relatively compact arrangement within an integrated circuit (IC). For example, the spintronic logic gates may perform logical operations with a smaller number of GSHE MTJ elements than a number of transistors required to perform the same logical operations with transistor-based logic gates. Also, while traditional combinational logic (i.e., logical circuits using transistor-based logic gates) must often employ separate sequential logic (e.g., latches, flip-flops, etc.) to store bit states resulting from the logical operations, the GSHE MTJ elements (i.e., the same elements used to perform the logical operations) may also operate as non-volatile memory to store bit states resulting from the logical operations. Therefore, not only can spintronic logic gates be used to fabricate more compact ICs (e.g., sequential state machines), the spintronic logic gates may also increase processing speeds and simplify IC designs.
In an example circuit or gate using spintronic logic a charge current generation circuit is coupled to a GSHE MTJ element to generate a charge current representing an input bit set. The input bit set may include one or more input bit states for a logical operation. A GSHE MTJ element may be initialized or preset to a preset state in a preset phase, prior to the logical operation. A threshold current level corresponding to the logical operation may be set for the GSHE MTJ element. In a compute phase, a GSHE spin current is generated in response to the charge current generated and the logical operation on the input bit set is performed, wherein the logical output bit state is set based on the preset state and whether the GSHE spin current exceeds threshold current level.
Spintronic circuits or gates can include several such GSHE MTJ elements, which may be cascaded in series or parallel and coupled to the charge current generation circuit. Accordingly, staged or pipelined operations can be performed, based on the characteristic of the GSHE MTJ elements to not only compute the logical output bit state but also hold or store the logical output bit state. For example, in a pipelined operation, the logical output bit state from a previous pipeline stage may be used for an input bit set in a following pipeline stage. Thus, the spintronic circuits using GSHE MTJ elements do not require additional latches or flip-flops which are seen in MOS based circuit designs for implementing pipelined or staged operations. Accordingly, significant power and area savings can be realized using spintronic logic gates.
However, the spintronic logic gates are also susceptible to undesirable charge or current paths which may arise in the various phases of logical operations. For some spintronic logic circuits, a reverse charge path may be created wherein a preset current used to establish the preset states may flow back to the charge current generation circuit or other input circuitry used to provide the input bit set to the spintronic logic gates. In some cases, it is possible for the charge current intended to write a spintronic logic gate in one pipeline stage to flow into an unintended pipeline stage. These charge or current paths are undesirable and may lead to incorrect operations or breaks in functionality of the spintronic logic circuits using GSHE MTJ elements.
Existing approaches to solving the undesired current paths are inefficient and/or ineffective. For example, one approach involves adding additional control lines or additional pipeline stages to separate the intended pipeline stage and the unintended pipeline stage in an effort to mitigate the flow of current from the intended pipeline stage to the unintended pipeline stage. However, such implementations significantly increase area and power and may also reduce speed of operation. Moreover, such implementations do not overcome the issues of undesirable current paths created due to the preset current flowing back into the input circuitry.